1. Field of the Invention
The present invention relates to an all optics type semiconductor image storage apparatus, and an all optics type semiconductor logical operation apparatus, and in particular, to an all optics type semiconductor image storage apparatus and methods for storing and erasing an image, using all light signals by means of a semiconductor diode device having a superlattice structure, and also to an all optics type semiconductor logical operation apparatus and a method for use in a logical operation method for executing a logical operation, using all light signals by means of a semiconductor diode device having a superlattice structure.
2. Description of the Prior Art
An all optics type storage apparatus of a first prior art is disclosed in, for example, a prior art reference document 1 of T. H. Barnes et al., "Bistable optically writable image memory using optical feedback", Optical Review, Vol.2, No.2, pp.103-105, 1995". This first prior art discloses an image storage operation executed by taking advantage of a change of the orientation of liquid crystals occurred when light is applied to its LCD screen. This storage apparatus employs a dual-beam interferometer which has an optical feedback operation exhibiting a threshold operation, a hysteresis operation and a bistable operation.
An all optics type logical operation apparatus of a second prior art is disclosed in, for example, a prior art reference document 2 of D. C. Burns et al., "A 256.times.256 SRAM-XOR pixel ferroelectric liquid crystal over silicon spatial light modulator", Optics Communications Vol. 119, pp.623-632, 1995". This second prior art is a spatial optical modulator whose address is designated electrically. This optical modulator is formed based on a hybrid technique for mounting ferroelectric liquid crystals on a silicon substrate, and it is provided with an array of 256.times.256 pixels operating at a frame rate balanced in charge of 2.1 kHz at maximum. A pixel circuit provided with a static random access memory (referred to as a SRAM hereinafter) latch circuit and an exclusive OR (referred to as an XOR hereinafter) gate has an excellent capability in designing one transistor for general use.
The first prior art has had such a problem that the apparatus has a complicated construction, a relatively great pixel size of 33 .mu.m.times.33 .mu.m and a relatively slow response speed of 50 msec. to 100 msec. The second prior art has had such a problem that the apparatus thereof requires an external electrode, a great pixel size of 40 .mu.m.times.40 .mu.m and a relatively slow response speed of 50 ms to 100 msec.